Interrupt arriving at the same time

I use FreeRTOS in Cortex-M3 architecture. My question is: 1 When Systick interrupt and other interrupt arriving at the same time, How FreeRTOS works? 2 If other interrupt preempts Systick interrupt when they arriving at the same time, Systick handler will be deffed. Whether to set the Systick priority highest to ensure the accuracy of the System tick?

Interrupt arriving at the same time

1 When Systick interrupt and other interrupt arriving at the same time, How FreeRTOS works?
How that works is dependent on the hardware (Cortex-M in this case). FreeRTOS is just software and cannot change how the hardware functions – so the answer is in the hardware reference manuals.
2 If other interrupt preempts Systick interrupt when they arriving at the same time, Systick handler will be deffed. Whether to set the Systick priority highest to ensure the accuracy of the System tick?
The SysTick must be the lowest priority interrupt. Again the hardware will take care of it for you – and you will only get into a time slippage issue if you are executing an interrupt handler that takes more than one entire tick interrupt time to execute (that is – more than the time between two tick interrupts). Regards.

Interrupt arriving at the same time

Other tasks want a definite time delay, but the time slippage issue affects accuracy of the delay time. How does such question solve? About the SysTick priority explanation, has not explained in FreeRTOS tutorial Cortex-M3 edition , where can I get information about the SysTick interrupt explanation? Regards.

Interrupt arriving at the same time

By the way, what does Regards mean? my mother tongue is not English. Thanks!

Interrupt arriving at the same time

Other tasks want a definite time delay,
The accuracy of any delay period can be specified with a granularity of 1 tick period. That is because the next tick interrupt that occurs after requesting the delay is taken as the first tick of the delay. So, if you ask for a delay immediately before a tick interrupt occurs then the first delay period will be a tiny fraction of one tick. Likewise, if you ask for a delay immediately after a tick interrupt occurs the first period of the delay will be one complete tick period.
but the time slippage issue affects accuracy of the delay time. How does such question solve?
As per my previous post – unless you are writing interrupt service routines that take more than one entire tick period to execute (so potentially two ticks occur during the execution of a single interrupt service routine) then there is no time slippage issue. If you interrupt genuinely do take that long then I would suggest drastically re-architecting your system as the goal should be for interrupt to be as short as feasibly possible – the deferred interrupt description in the book text shows you how to do that. >
About the SysTick priority explanation, has not explained in FreeRTOS tutorial Cortex-M3 edition , where can I get information about the SysTick interrupt explanation?
I’m not sure exactly what the book says about this, hopefully it is in the code comments. Regards.

Interrupt arriving at the same time

As a noun it means “best wishes” (used to express friendliness in greetings). In formal letters (before the days of email) a sign off would be either “yours sincerely”, or “yours truly” (depending on how the letter starts I think). “best regards” being a slightly less formal version. Its a bit old fashioned, and I just abbreviated it to “regards”.

Interrupt arriving at the same time

The other point about the slippage, unless the task was the highest priority task, it could be delayed by other tasks, and thus not restart at exactly the “right” time. And, even if it was the highest task, that other interrupt that delayed the sys tick, would have delayed the task too, even if the systick had been highest priority and switched to it.

Interrupt arriving at the same time

Thank you very much!

Interrupt arriving at the same time

I am so glad that you can help me to sovle the problem.