I’m a  little confused about  the different between taskENTER_CRITICAL and taskDISABLE_INTERRUPTS. I read the user manual, it said “they working by disabling interrupt……Pre-emptive switch can only occur from interrupt, so as long as interrupt remains disabled, the task called the taskENTER_CRITICAL can guaranteed to remain in running state “. From my understanding, both of them can result in disabled interrupt and context switch.  Any tips?

ENTER_CRITICAL() keeps a count of the call nesting and is the only one you should use really. It normally calls DISABLE_INTERRUPTS internally. Some but not all ports can still context switch with interrupts disabled, but not from in a preemptive way because with interrupts being disabled they cannot be preempted.

thanks davedoors  for your answer, but I am still not very clear. Is there any ‘extra benefit’ ENTER_CRITICAL could provides, besides disabled interrupt. They seem to be the same to me. I can’t tell the differences betweens them. Then I start wonder why do I need two different interface, if they share nearly the same features.  I guess there should be something unknown to me.

The big difference is the ENTER/EXIT Critical takes into account nesting, Enable/Disable interrupt do not. Thus ENTER
  /* Interrupts now disabled */
ENTER
EXIT
/* Interrupts still disabled */
EXIT
/* unwound all the critical sections, so interrupt now enabled */ While with DISABLE you would get DISABLE
/* Interrupts now disabled */
DISABLE ENABLE
/* Interrupts now reenabled even though we disabled twice */
ENABLE

Aha~ thanks~ I got it now. That’s the reason I saw push and pop assembly code in one of the porting file for ENTER_CRITICAL and EXIT_CRITICAL

Critical sections should not be storing the “stacking” of them on the stack, but tend to use a counter. Some ports may use push/pop to access a status/control register. One thing to note is that a critical section may not disable ALL interrupts, but may just disable those interrupts at a level which is allowed to interact with the kernel, and this is sometimes done by setting the current interrupt priority level in the hardware.